Sample and hold channels typically use a switch to capture a signal and a storage element to hold the captured or sampled signal. The switch is usually a semiconductor device such as a transistor, e.g. an FET, and the storage device is a capacitor. An attenuator circuit receives the input signal and scales it to the amplitude range acceptable to the system. These sampling transistors are, however, not perfect switches: their on resistance and the capacitance seen by the channel are both non-linear functions of the input voltage being sampled. These non-linearities, particularly at high speed, lead to distortion of the sampled signal. To improve this a back gate circuit has been introduced. The scaled input voltage at the output of the attenuator circuit is split: part goes to the main sample and hold channel and part goes to the back gate circuit. The back gate circuit connects the input signal to the back gate during the sample part of the operation so that the back gate voltage tracks the voltage applied to the main transistor terminals. This minimizes the voltage differential across the transistor junction and thus lowers the on resistance of the device thereby reducing the non-linear effects. Increasing the size of the switch also does this but there comes a point at which the improvements due to reducing the on resistance are less valuable than the deterioration due to increasing the non-linear capacitance. When the back gate of the MOS device is switched, the non-linear capacitance from the channel to the back gate disappears, since the channel and back gate are at the same potential, but instead the capacitance from the back gate (p-well) to the substrate (n-type) is seen. This capacitance is usually more non-linear since the doping concentrations in these two regions are generally lower.